The TLV8x3 family of supervisory circuits provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems.
During power on, RESET asserts when the supply voltage (VDD) exceeds 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time (td(typ) = 200 ms) starts after VDD exceeds the threshold voltage, VIT. When the supply voltage drops below the VIT threshold voltage, the output is active (low) again. All the devices in this family have a fixed sense-threshold voltage (VIT) set by an internal voltage divider.
